Theoretical Research on Time Scaling in Multi-layer Electronic Systems-Exploring Huawei's "Ta (τ) Law"

Abstract

Over the past six decades, the semiconductor industry has advanced through the geometric scaling paradigm of Moore's Law—achieving smaller transistors, higher integration density, and lower unit costs. However, as manufacturing processes approach dual physical and economic ceilings (post-7 nm technology sees rising transistor costs instead of falling reductions, while EUV depreciation dominates wafer costs), the marginal returns of purely "size reduction" strategies have sharply declined. In 2026, Hua Weitingbo's team formally proposed the "Tau Scaling Theory (τ Scaling/Time Scaling Theory for Multi-Layer Electronic Systems)," advocating systematic time-scale compression using the time constant τ as the unified optimization goal across multiple system layers—from picosecond-level transistor switching to second-level system loads spanning approximately 12 orders of magnitude. Building on this theoretical framework and industrial context, this paper rigorously establishes a hierarchical time-scale decomposition model for multi-layer electronic systems, derives τ expressions and scaling relationships at each layer, and validates through MATLAB numerical simulations: when geometric scaling reaches its limit, equivalent system performance can still exhibit nearly exponential growth by leveraging four key strategies—parasitic reduction, logic folding (key path shortening), 3D interconnect topology optimization, and full-stack co-scheduling—to compress τ. This paper simultaneously establishes a conceptual framework linking τ scaling with classical Dennard scaling, the Rent rule, and the RC delay model, while providing a quantitative discussion on the applicable boundaries of this paradigm.